HAL SRAM migration: List of applicable concepts ¶
This section provides information about the HAL SRAM applicable architecture concepts.
Concepts for SRAM ¶
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Concept |
Description |
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The
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Removal and conversion of init structure to configuration structure |
The init structure
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The handle structure
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The init structure
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The
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Two functions to set and get user data are available:
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The SRAM state machine has been revised as follows:
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The input parameter checks using assertions have been added to the APIs. |
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All TypeDef parts of the HAL SRAM driver have been removed and replaced by
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Const keywords have been added to non-modifiable pointers to ensure that either the pointer itself or the data it points to cannot be modified. This enhances code safety and readability, prevents unintended modifications, and renders code more robust and maintainable. |
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The parameters and state are checked using
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Rename LL core drivers to stm32_ppp_core.h/.c to avoid confusion with user LL drivers. |
The core driver name is changed from
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Add HAL PPP Services for Drivers with Handle to Retrieve Corresponding Peripheral Clock Frequency. |
The HAL SRAM driver provides a new API to retrieve the clock frequency:
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Replace Finite Parameter Defines (Including PPP Instances) with Enum Types at HAL Levels. |
Finite parameters (including SRAM instances) have been converted into enumerated types (enums) at HAL level. This improves code readability, maintainability, and type safety. |
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The conditional compilation flag
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Add ASSERT_DBG_STATE macro controlled by USE_ASSERT_DBG_STATE conditional. |
The conditional compilation flag
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Other HAL SRAM changes ¶
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Concept |
Consideration |
|---|---|
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Use the sub-bank as the unitary instance instead of providing the base address and the bank offset |
The new enumeration
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Split the configuration into Static configuration structure and Memory configuration structures |
The
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Add SRAM write protection state in the handle |
The
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Remove WriteOperation from SRAM configuration structure |
When needed the user call directly the corresponding API. The WriteOperation is removed from configuration, the write protection is enabled by default. |
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Remove process APIs as they depends of user application |
There is no specific FMC hardware configuration needed for DMA requests, as read and write operations are directly accessible by the user. |
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Add API to check the status of write protection |
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Change timing parameters unit from cycle to ns |
The static API is added to convert these values before setting them in the FMC register. |
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Remove
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DMA functionality is separated from SRAM because the memory is memory-mapped and does not require dedicated DMA handling. |
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Remove extended mode
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Bank1 is selected directly without requiring explicit , the instance will be used to sub-banks. |